1. Field of the Invention
The present invention relates to an electrode structure of a semiconductor element and, particularly, to an electrode structure suitable for a high density integration of semiconductor elements on a semiconductor chip.
2. Description of Related Art
In order to respond to recent requests of grade-up of electronic equipments, reduction of size and weight thereof and increase of an operation speed thereof, semiconductor devices based on new concepts are having been developed. For example, a reduction of size and weight of an electronic equipment has been realized by reducing size and thickness of semiconductor devices integrated on a semiconductor chip at high density.
FIG. 1 is a plan view of a semiconductor element formed on a chip and constituting a semiconductor device and FIG. 2 shows a portion of the semiconductor element in enlarged scale. The semiconductor element 1 includes an internal circuit 2 and pads 3 for electrodes, arranged in a peripheral portion of the internal circuit 2. The semiconductor element 1 is connected externally by connecting the pads 3 to external lead terminals of a package through bonding wires. The bonding wires are connected to the pads 3 by pressing the bonding wires to the pads 3 while applying heat and ultrasonic vibration to the connecting points therebetween. Such connection method is referred to as "wire bonding".
In a recent semiconductor element, particularly, a semiconductor element for logic operation, the number of signal lines, which can not be used commonly, is increased with increase of integration density for improving performance thereof. Therefore, it is necessary to arrange a number of pads in an outer peripheral portion of the semiconductor element, for exchange of signals between an internal portion of the semiconductor element and an outside thereof. Further, in order to stabilize an operation of the semiconductor element, it is necessary to increase the number of not only pads for power sources but also those for grounding.
On the other hand, the size and weight of a whole semiconductor device constructed by integrating a plurality of such semiconductor elements on a single chip is also being reduced. In such case, since the reduction of size and weight of the semiconductor device itself is reduced with increase of integration density of the internal circuits of the semiconductor elements and an area of each semiconductor element, which is required for arranging an increased number of pads, is limited, it is necessary in order to increase the number of pads to reduce a pitch (P in FIG. 2) between adjacent pads.
Further, the size of a transistor, which is a minimum unit of a semiconductor device, is being reduced in concomitance with improvement of performance of a fabrication apparatus for fabricating the semiconductor device and improvement of a fabrication process thereof and, therefore, the size of an internal circuit of each of semiconductor elements constituting the semiconductor device is also being reduced. As a result, the size of the whole semiconductor element is reduced and, so, the size of each of the pads to be arranged in the semiconductor element has to be reduced.
Under the circumstances, the area of each pad defined by X and Y and the pitch P are reduced from X=Y=80 .mu.m and P=100 .mu.m to X=Y=60 .mu.m and P=80 .mu.m, respectively, as shown in FIG. 2.
FIGS. 3 and 4 are cross sections showing examples of a conventional structure of a peripheral portion of a pad of a semiconductor element, respectively. In these examples an oxide film 12 of such as SiO.sub.2 is formed on a semiconductor substrate of such as Si and an insulating film 13 of such as SiO.sub.2 or SiOF is formed on the oxide film 12. Further, a wiring 14 of such as Cu is formed on the insulating film 13. An insulating film 15 is formed on the wiring 14 and pads 3 of such as Al are formed on the insulating film 15. A via-hole 16 is formed in the insulating film 15. The via-hole 16 is filled with a metal such as W, Al or Cu to electrically connect the wiring 14 to the pad 3. In the example shown in FIG. 3, the via-hole 16 is formed such that the via-hole 16 is located in substantially a center of the pad 3 and, in the example shown in FIG. 4, the via-hole 16 is located in the vicinity of an end portion of the pad 3. There may be a case where a plurality of via-holes are provided for each pad. A periphery of the pad 3 are protected by a metal film of such as TiN or Ti covering it and other area of the semiconductor element than the pad area is usually protected by an insulating film 17 of such as SiO.sub.2 covering it. The pad 3 is electrically connected to an external lead terminal of a package through a wire 18.
The connection between the pad 3 and the wire 18 is performed by thermosonic wire bonding, which connects metal materials by pressing one of them to the other while using pressure, heat and ultrasonic vibration simultaneously. That is, a top end of a gold or copper wire supplied through a capillary is balled by heating it by an electrictorch and the ball is pressed and connected to the pad while applying ultrasonic wave thereto.
In the electrode structures shown in FIGS. 3 and 4, however, the fabrication yield of semiconductor device is reduced due to thermosonic wire bonding, that is, the producibility of semiconductor device becomes degraded.
That is, when the wire is mechanically pressed to the pad in order to perform the thermosonic wire bonding, there is a possibility that the pressing force is propagated to a connecting portion between the pad and the underlying insulating film and the connecting portion is damaged thereby. Such phenomenon does not cause substantial problem if the size of the pad is relatively large and the pitch of the pads is relatively large. However, when the size and pitch of the pads are reduced with reduction of the size of semiconductor element and increase of the integration density, the size of the ball formed on the top of the wire must be reduced. Therefore, stress exerted on a unit area of the pad is increased, so that breakage and damage of the pad and the underlying insulating film tend to occur. This problem may cause the pad to be easily peeled off, resulting in reduction of fabrication yield of semiconductor device, that is, degradation of the producibility.